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Beilstein J. Nanotechnol. 2014, 5, 964–972, doi:10.3762/bjnano.5.110
Figure 1: Conceptual diagram of a SiNW FET.
Figure 2: Typical measurement system.
Figure 3: Shape of the power spectrum of IRS from 5-bit length shift register.
Figure 4: Schematic of the applied SiNW FET device.
Figure 5: SEM image of the SiNW FET device. The scale bar is 20 µm.
Figure 6: Ids–Vds DC measurement results.
Figure 7: Ids–Vg DC measurement results.
Figure 8: Conceptual diagram of the measurement setup.
Figure 9: Simplified schematic of the measurement amplifier.
Figure 10: Generated excitation sequence; a) sample in the time domain, and b) (scaled) energy content.
Figure 11: Admittance spectroscopy for gate voltages from 1.0 V to 3.0 V.
Figure 12: Admittance spectroscopy for gate voltages of 2.0 V and 2.2 V.